This invention relates generally to ferroelectric memories. More particularly, the present invention relates to a method of fabricating a ferroelectric capacitor stack (bottom electrode, ferroelectric dielectric, top electrode) for use in an integrated circuit ferroelectric memory.
In general, prior art integrated circuit ferroelectric memories have two major problems. One of these problems is increased surface topology, which leads to manufacturability problems such as metal step coverage and the like. The second problem is related to xe2x80x9cline degradationxe2x80x9d, which generally refers to the loss of functionality primarily due to damage experienced by the ferroelectric capacitor dielectric during the many processing steps required to fabricate a packaged ferroelectric memory. A main source of the damage can be traced to exposure of the ferroelectric capacitor dielectric to hydrogen. Prior art structures and methods of dealing with hydrogen exposure and the resultant damage and loss of functionality included placing barrier materials such as PZT or other barrier materials directly over the ferroelectric capacitor. While these prior art methods somewhat reduced line degradation, they can become compromised when the contact to the top electrode is formed. The top electrode contact becomes the entrance of a pathway for hydrogen to still attack the ferroelectric dielectric layer that is located laterally beneath the top electrode.
What is desired is a device structure for an integrated circuit ferroelectric memory that is both planar and insensitive to hydrogen-induced line degradation.
It is, therefore, a principal object of the present invention to construct a compact and manufacturable ferroelectric capacitor stack for use in an integrated circuit ferroelectric memory.
It is an advantage that the capacitor stack structure of the present invention does not require a top electrode contact laterally located over the switching ferroelectric layer, and therefore line degradation is significantly minimized.
It is another advantage of the invention that bottom electrode contact to the transistor source/drain is made after high temperature annealing, which helps to prevent silicon poisoning of the bottom electrode.
It is another advantage of the present invention that the resultant ferroelectric memory structure has reduced surface topology because of the planarizing nature of the deposition technology used in at least one of the layers such as CSD (chemical solution deposition) or MOCVD metalorganic chemical vapor deposition).
It is another advantage of the present invention that a ferroelectric capacitor can be formed directly over a planarized transistor source/drain when an appropriate barrier material is included to prevent interaction of the bottom electrode and the transistor contact structure.
According to a first method of the present invention, a ferroelectric capacitor stack for use with an integrated circuit transistor in a ferroelectric memory cell is fabricated by: forming a first dielectric layer over the integrated circuit transistor; forming a bottom electrode over the first dielectric layer, the bottom electrode having a hole located over a first source/drain of the integrated circuit transistor; forming a second dielectric layer over the first dielectric layer and bottom electrode; forming a hole in the second dielectric layer to provide access to the bottom electrode; forming a ferroelectric plug in the hole in the second dielectric layer; forming a top electrode over the second dielectric layer and ferroelectric plug; forming a third dielectric layer over the second dielectric layer and top electrode; forming a first via through the first, second, and third dielectric layers, and through the hole in the bottom electrode, the via having sufficient width to provide access to a lateral edge of the bottom electrode hole; forming a second via through the first, second, and third dielectric layers to provide access to a second transistor source/drain; forming a third via through the third dielectric layer to provide access to the top electrode; metalizing the first via; metalizing the second via; and metalizing the third via.
A second method of the present invention is similar to the first method, wherein the hole in the second dielectric layer may be sloped, if desired.
According to a third method of the present invention, a ferroelectric capacitor stack for use with an integrated circuit transistor in a ferroelectric memory cell is fabricated by: forming a first planarized dielectric layer over the integrated circuit transistor; forming first and second vias in the first planarized dielectric layer to provide access to first and second source/drains of the integrated circuit transistor; forming first and second metal plugs in the first and second vias, respectively; forming a bottom electrode over the second metal plug; forming a second planarized dielectric layer over the first planarized dielectric layer and bottom electrode; forming a hole in the second dielectric layer to provide access to the bottom electrode; forming a ferroelectric plug in the hole in the second dielectric layer; forming a top electrode over the second dielectric layer and ferroelectric plug; forming a third planarized dielectric layer over the second dielectric layer and top electrode; forming a first via through the second and third planarized dielectric layers to provide access to the first metal plug; forming a second via through the third planarized dielectric layer to provide access to the top electrode; metalizing the first via; and metalizing the second via.
According to a fourth method of the present invention, a ferroelectric capacitor stack for use with an integrated circuit transistor in a ferroelectric memory cell is fabricated by: forming a first planarized dielectric layer over the integrated circuit transistor; forming first and second vias in the first planarized dielectric layer to provide access to first and second source/drains of the integrated circuit transistor; forming first and second metal plugs in the first and second vias, respectively; forming a second planarized dielectric layer over the first planarized dielectric layer and first and second metal plugs; forming a bottom electrode over the second planarized dielectric layer, the bottom electrode having a hole located over the second metal plug; forming a ferroelectric layer on the bottom electrode; forming a patterned third planarized dielectric layer having a hole to provide access to the ferroelectric layer; forming a top electrode over the ferroelectric layer; forming a fourth planarized dielectric layer over the third dielectric layer and top electrode; forming a first via through the second, third, and fourth planarized dielectric layers to provide access to the first metal plug; forming a second via through the second, third, and fourth planarized dielectric layers, and through the hole in the bottom electrode, the via having sufficient width to provide access to a lateral edge of the bottom electrode hole; forming a third via through the third planarized dielectric to provide access to the top electrode; metalizing the first via; metalizing the second via; and metalizing the third via.
According to a fifth method of the present invention, a ferroelectric capacitor stack for use with an integrated circuit transistor in a ferroelectric memory cell is fabricated by: forming a first dielectric layer over the integrated circuit transistor; forming a bottom electrode over the first dielectric layer, the bottom electrode having a hole located over a first source/drain of the integrated circuit transistor; forming a ferroelectric layer on the bottom electrode; forming a second dielectric layer over the first dielectric layer and bottom electrode; forming a hole in the second dielectric layer to provide access to the ferroelectric layer; forming a top electrode over the ferroelectric layer; forming a planarized dielectric layer over the second dielectric layer and top electrode; forming a first via through the first, second, and planarized dielectric layers to provide access to the first source/drain; forming a second via through the first, second, and planarized dielectric layers, and through the hole in the bottom electrode, the via having sufficient width to provide access to a lateral edge of the bottom electrode hole; forming a third via through the planarized dielectric layer to provide access to the top electrode; metalizing the first via; metalizing the second via; and metalizing the third via.
According to a sixth method of the present invention, a ferroelectric capacitor stack for use with an integrated circuit transistor in a ferroelectric memory cell is fabricated by: forming a bottom electrode over a first source/drain of the integrated circuit transistor; forming a first planarized dielectric layer over the integrated circuit transistor and bottom electrode; forming a hole in the first dielectric layer to provide access to the bottom electrode; forming a ferroelectric plug in the hole in the first dielectric layer; forming a top electrode over the ferroelectric plug and first dielectric layer; forming a second planarized dielectric layer over the first planarized dielectric layer and top electrode; forming a first via through the first and second planarized dielectric layers to provide access to a second source/drain; forming a second via through the second planarized dielectric layer to provide access to the top electrode; metalizing the first via; and metalizing the second via.
After the top electrode is formed in each of the methods of the present invention, an optional ferroelectric encapsulation layer may be formed. This layer serves as a hydrogen barrier, and may patterned to be coextensive with the capacitor ferroelectric layer, to overlap the top electrode, or to cover the entire surface of the ferroelectric memory, if desired.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings.